Design and Verification of VHDL Code for FPGA Based Slave VME Interface Logic - TechRepublic

Design and Verification of VHDL Code for FPGA Based Slave VME Interface Logic

Last Updated: February 12, 2022 Format: PDF

Versa Module Europa (VME) bus is used in various applications in order to ensure safety and security. VME64x based Real Time Computer (RTC) system with various types of Input /Output (I/O) hardware modules is being designed and developed for use in various safety critical and safety related Instrumentation & Control (I&C) systems. Analog Output Card (AOC) is one of the I/O hardware modules as part of VME64x RTC development. The AOC uses Field-Programmable Gate Array (FPGA) as VME bus system controller. This paper discusses the design and development of a VME64x bus controller so as to meet the required specifications correctly.

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