Design of BIST with Low Power Test Pattern Generator

In this paper, low power Built-In-Self-Test (BIST) is implemented for 32 bit Vedic multiplier. This paper is to reduce power dissipation in BIST with increased fault coverage. Various methods of pattern generation are compared keeping in view of power consumption. In this test pattern generation the seed value is changed every 2m cycles. For this purpose m bit binary counter & gray code generator is used. Signature analysis is done with the help of Multiple Input Signature Register (MISR).