Design of Low Power 8 Bit GDI Magnitude Comparator
Low power 8 bit GDI magnitude comparator is proposed in this paper which has an advantage of minimum power dissipation, reduced propagation delay and less number of transistors required as compare to conventional CMOS magnitude comparator. Proposed GDI magnitude comparator is designed at 100MHz frequency with 1.8 v supply voltage using 180nm technology using CADENCE VLSI EDA tools. The performance analysis of proposed GDI magnitude comparator is also compared with conventional CMOS comparator, transmission gate comparator and NMOS pass gate comparator.
Subscribe to the Innovation Insider Newsletter
Catch up on the latest tech innovations that are changing the world, including IoT, 5G, the latest about phones, security, smart cities, AI, robotics, and more. Delivered Tuesdays and Fridays