Network-on-Chip (NoC) is an advance design method of communication network into System-on-Chip (SoC). It provides solution to the problems of traditional bus-based SoC. It is widely considered that NoC will take the place of traditional bus-based design and will meet the communication requirements of next SoC design. A router is the key component and called as the communication backbone in NoC. This paper presents NoC router architecture which has low latency and requires less area. The design is implemented in VHDL and simulated in Xilinx ISE design suite 13.1.