Dynamic Power Reduction of Synchronous Digital Design by Using of Efficient Clock Gating Technique

Clock gating is an effective method of reducing the dynamic power consumption in synchronous circuits. One of the ways to achieve this is by masking the clock that goes to the idle portion of the circuit. In this paper, the authors will present a comparative analysis of existing clock gating techniques on some synchronous digital design like ALU (Arithmetic Logical Unit), etc. Also, a new clock gating technique that provides more immunity to the existing problem is available in this paper.