Efficient Design of Fixed Width Modified Post Truncated Booth Multiplier

Complex arithmetic operations are widely used in Digital Signal Processing (DSP) applications. The techniques are used to implement the direct recoding of the sum of two numbers in its Modified Booth (MB) form introduce a structured and efficient recoding technique and explore three different schemes by incorporating them in FAM designs. Comparing them with the FAM designs, that use existing recoding schemes, this paper yields considerable reductions in terms of critical delay, hardware complexity and power consumption of the FAM unit. In case of large multiplication there may be chance of occurring truncation errors in this FAM unit.

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