In this paper, the authors aimed to implement the RSA algorithm 1024-bit in the FPGA with the help of Verilog HDL. The RSA algorithm using FPGA can be used as a standard device in the secured communication system. A simple nested loop addition and subtraction have been used in order to implement the RSA operation. The modification of RSA algorithm includes pipeline and data dependence computational block. This results in very low frequency, high speed, low power consumption and low cost compared to other algorithm methods.