In this paper, the authors propose a compact AES (Advanced Encryption Standard) algorithm to achieve less slice consumption of FPGA. Proposed design is based on iterative round looping architecture. S-box is implemented using composite field arithmetic which requires less area than lookup table. They used same s-box for key expansion block. This design supports 128-bits key size. It uses 8-bit data path to decrease the parallelism of operations and therefore reduces the hardware utilization. Synthesis of their complete design is done using Xilinx ISE 14.5 and implemented on Spartan 3 FPGA using VHDL language.