FPGA Implementation of a New Parallel FIR Filter Structures
In recent days filters with large lengths are started to use. So parallel processing is essential at any cost. In this paper, the authors propose new parallel FIR filter structures, which are beneficial to symmetric coefficients in terms of the hardware cost, under the condition that the number of taps is a multiple of 2 or 3. The proposed parallel FIR structures use symmetric property to reducing half the number of multipliers in sub filter section at the expense of additional adders in preprocessing and post processing blocks.