FPGA Implementation of Efficient Carry-Select Adder Using Verilog HDL

Carry SeLect Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This paper uses the logic operations involved in conventional CSLA and dual RCA’s based CSLA, Binary to Excess Converter (BEC)-based CSLA, CLB based CSLA are analyzed to study the data dependence and to identify redundant logic operations. The authors have eliminated all the redundant logic operations present in the conventional CSLA and proposed a new logic formulation for CSLA.