A priority interrupt controller is a hardware designed chip which acts as an overall system manager to efficiently handle the multiple interrupts that tend to occur from the varied number of peripheral devices. Hence, it relieves the system’s CPU from the task of polling in a multi-level priority system. This paper deals with implementation of a priority interrupt controller using Verilog language. During the implementation, the Verilog code has been written for all the internal registers of the priority interrupt controller so, that it can accomplish its task of prioritizing the various interrupts and thereby increasing the efficiency of the processor.