FPGA Implementation of Vedic Multiplier

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Provided by: International Association of Engineering and Management Education (IAEME)
Topic: Hardware
Format: PDF
As multipliers plays an important role in many fields like signal processing, embedded systems, so the demand to have an efficient and fast multiplier is increasing. This paper presents an efficient algorithm of Vedic multiplier. Vedic multiplier as compared to other multipliers like array multiplier, Wallace tree multiplier, booth multiplier, modified booth multiplier etc. carry out the multiplication of two numbers very efficiently and Vedic multiplication process as compared to others is also fast. This paper briefly describes the methods used for Vedic multiplication and the flow of multiplication with the help of flow chart.
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