For high data rate wireless communications they use Orthogonal Frequency Division Multiplexing (OFDM) due to its high spectral efficiency and low computational complexity. It gives the architecture of an optimized complex matrix inversion using Gauss-Jordan (GJ) elimination in Verilog with single precision floating-point representation. The GJ-elimination algorithm uses a single precision floating point arithmetic components and control unit for performing necessary arithmetic operations. The proposed architecture implements the GJ-elimination algorithm for complex matrix element sequentially. Matrix inversion using GJ-elimination improves the frequency when compared with QR decomposition algorithm. The design is targeted on XC5VLX50T Xilinx FPGA.