Implementation of Decoders for High Speed Memory Applications

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Provided by: MIT Publications
Topic: Hardware
Format: PDF
In this paper, the authors are to design all the necessary components required to form a 5 - 32 bit decoder using NOR logic at 180 nm & 350 nm technologies. Most important aspect is to size the basic component of decoder (i.e., transistor) for a particular load. Discrete quantities of information can be represented in digital systems with binary codes. A binary code of n bits is capable of representing it up to 2n distinct elements of given information. A decoder is a combinational circuit that transforms binary information from n input lines to a maximum of 2n unique output ways. If the n-bit decoded information has unused or don't care combinations, the decoder output will have less than 2n outputs.
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