Implementation of Low Power and High Speed Multiplier-Accumulator Using SPST Adder and Verilog

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Provided by: International Journal of Modern Engineering Research (IJMER)
Topic: Hardware
Format: PDF
In this paper, the authors proposed a new architecture of Multiplier and ACcumulator (MAC) for high-speed arithmetic and low power. Multiplication occurs frequently in finite impulse response filters, fast Fourier transforms, discrete cosine transforms, convolution, and other important DSP and multimedia kernels. The objective of a good Multiplier and ACcumulator (MAC) is to provide a physically compact, good speed and low power consuming chip. To save significant power consumption of a VLSI design, it is a good direction to reduce its dynamic power that is the major part of total power dissipation.
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