Implementation of Vedic Complex Multiplier for Digital Signal Processing

Basic and heart of all (Digital Signal Processing) DSP are its multiplier. Speed of multiplier determines the speed of the DSP. In DSP, fast multiplication is very important for convolution, Fourier transforms and multiplication is the most basic operation with deep and thorough arithmetic computation. Latency and throughput are two important parameter associated with multiplication performed in DSP. In this paper, VHDL implementation of complex number multiplier using ancient Vedic mathematic. By using “Vedic mathematic” concept can skip carry propagation delay. The “Urdhva tiryakbhyam” sutra was selected for implementation since it is applicable to all cases of multiplication.

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International Journal of Engineering Research and Applications (IJERA)