Low Power VLSI CMOS Design by DCG Technique

The demand for power-sensitive design has grown significantly in recent years due to tremendous growth in portable applications. Consequently, the need for power efficient design techniques has grown considerably. Several efficient design techniques have been proposed to reduce both dynamic as well as static power in state-of-the-art VLSI circuit applications. With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major bottleneck for microprocessor designs. Clock power is significant in high-performance processors. Deterministic Clock Gating (DCG) technique effectively reduces the clock power.

Resource Details

Provided by:
Institute of Research in Engineering and Technology (IRET)