Mapping of Multiple Data Flow Graphs of DSP Applications onto ASIC/Reconfigurable Architectures

In this paper, the authors present a novel technique for the mapping of set of DSP applications onto architectures targeting an ASIC/Reconfigurable implementation embedded on the same chip. Synthesis for such a hybrid implementation is carried out by developing a technique to partition the RTL structures corresponding to a set of DSP applications into a fixed base design part suitable for ASIC implementation and a non-base design that varies with the applications and suitable for FPGA implementation.