In this paper, the authors address the problem of minimizing the implementation cost of the Time-Multiplexed Constant Multiplication (TMCM) operation that realizes the multiplication of an input variable by a single constant selected from a set of multiple constants at a time. It presents an efficient algorithm, called ORPHEUS that finds a multiplierless TMCM design by sharing logic operators, namely adders, subtractors, adders/subtractors, and MUltipleXors (MUXes). Moreover, this paper introduces folded design architectures for the Digital Signal Processing (DSP) blocks, such as Finite Impulse Response (FIR) filters and linear DSP transforms, and describes how these folded DSP blocks can be efficiently realized using TMCM operations optimized by ORPHEUS.