Parallel FPGA Design of CA CFAR Algorithm
The authors propose a parallel implementation of the Cell Average Constant False Alarm Rate (CA-CFAR) algorithm in reconfigurable hardware. The design is based on a parallel processing scheme employing extensive data reuse and synchronized sliding windows over the input data sequence. A scalable parallel structure is designed and mapped on Xilinx Virtex II Pro technology. Synthesis and post place and route results from the Xilinx ISE toolset suggest a linear speedup and resource utilization. More specifically, a single CFAR implementation utilizes 1.4% of the VIRTEX II Pro XC2VP30 chip, providing a throughput of 974 Mbps.
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