Power Optimization of 8:1 MUX Using Transmission Gate Logic (TGL) with Power Gating Technique

In this paper, the authors aim at reducing power and energy dissipation in Transmission Gate Logic (TGL) multiplexer CMOS circuits comprise of reducing the power supply voltages, power supply current and delay with economical charge recovery logic. This paper designs an 8:1 multiplexer with CMOS Transmission Gate Logic (TGL) using the power gating technique, which reduces the leakage power and leakage current in active mode. Power gating technique uses TGL based on 8:1 multiplexer circuit which removes the degraded output.