Reordering Algorithm for Minimizing Test Power in VLSI Circuits

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Provided by: International Association of Engineers
Topic: Hardware
Format: PDF
Power consumption has become a crucial concern in Built-In Self-Test (BIST) due to the switching activity in the Circuit Under-Test (CUT). In this paper, the authors present a novel method which aims at minimizing the total power consumption during testing. This is achieved by minimizing the switching activity in the circuit by reducing the hamming distance between successive test vectors. In this paper, the test vectors are reordered for minimum total hamming distance and the same vector set is used for testing.
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