Journal of Theoretical and Applied Information Technology
In this paper, a novel hybrid ADC consisting of two-step quantizer which has flash ADC and SAR ADC along with resistor string DAC is designed and implemented. This hybrid ADC improves the speed by employing flash ADC and resolution and power reduction can be achieved by utilizing SAR ADC. The hybrid architecture carrying 12 bits as resolution, input frequency as 100MHz and sampling frequency is 1GHz. CMOS level schematic diagram of sub-blocks has been designed and implemented using Cadence Virtuoso 180nm technology at an operating voltage of 1.8 V.