RISC-V: What it is, and what benefits it can provide to your organization

RISC-V is an instruction set architecture for processors that offers innovative operational mechanisms. Learn about its background and the advantages it brings.

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RISC-V is an instruction set architecture which offers innovative operational mechanisms. Learn about its background and the advantages it brings.

Steven Levy's amazing novel Hackers: Heroes of the Computer Revolution is a must-read for any technologist (or layperson) enamored with the computing field. Focusing on the first true computer geeks at MIT in the late 1950s, the book explores in detail the primitive—quaint, really—hardware specs of the first computers which at the time could do relatively little but which paved the way to much greater feats. 

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Reading about the passion of the pioneers in the computing field—some of whom became so entranced by technology that it became an obsession—never fails to inspire me. As a result, optimizing hardware capabilities has long been a hobby of mine; tweaking and customizing to get the most out of system components to achieve the best results. 

One such element I recently came across is known as RISC-V, which is a unique computing instruction set architecture. Developed in 2010, RISC-V offers many advantages to consumers and businesses. 

I discussed these advantages with Mark Himelstein, CTO at RISC-V, an organization that seeks to promote the RISC-V instruction set architecture.

Scott Matteson: What is RISC-V?

Mark Himelstein: RISC-V is a free and open instruction set architecture (ISA) enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

Scott Matteson: What are the advantages of the ISA? 

Mark Himelstein: RISC-V has a variety of advantages including its openness, simplicity, clean-slate design, modularity, extensibility, and stability, unlike legacy ISAs that are decades old and not designed to handle the latest compute workloads. At RISC-V International, we continue to witness RISC-V:

  1. Enable innovation: RISC-V is a layered and extensible ISA so companies can easily implement the minimal instruction set, well defined extensions and custom extensions to create custom processors for cutting-edge workloads.
  2. Reduce risk and investment: By enabling companies to leverage established and common IP building blocks with the development community's growing set of shared tools and development resources.
  3. Provide the flexibility to customize processor: Since implementation is not defined at the ISA level, but rather by the composition of the SoC (system on a chip) and other design attributes, engineers can customize chipsets to be big, small, powerful or lightweight based on what devices need.
  4. Accelerate time to market through collaboration and open source IP reuse: RISC-V not only reduces development expenses, but also enables companies to get their designs to market faster.

At the end of the day, there are a few things that really matter: Having the ability to run the same application binaries on different implementations, and to be able to run the same os/hypervisor on different implementations. 

In addition to the many benefits RISC-V offers companies, the simple fixed-base ISA and modular fixed standard extensions also make it easy for researchers, teachers and students to leverage RISC-V to learn and push the boundaries of design. 

Scott Matteson: How does RISC-V work? How is it different from traditional ISAs?

Mark Himelstein: Whereas some closed, proprietary ISAs have costly licensing fees, the RISC-V ISA is free and open for use by anyone in all types of implementations without restriction. RISC-V was intentionally designed to have a small, fixed-base ISA along with modular fixed-standard extensions that work well for the majority of code. This leaves ample room for application-specific extensions, without interfering with the standard ISA core.

Having a simple base architecture helps prevent fragmentation while also supporting customization. Many companies are taking advantage of RISC-V to create custom processors designed to handle the power and performance requirements of newer workloads for (artificial intelligence) AI, (machine learning) ML, (Internet of Things) IoT, and (virtual reality) VR/(augmented reality) AR applications.

Scott Matteson: What are some subjective daily examples of use for consumers and businesses?

Mark Himelstein: RISC-V is ideal for a wide variety of embedded applications, from IoT applications to computer devices (such as disks) to automotive applications and computer controllers (such as graphics). 

RISC-V is also being used for custom processors targeted to applications from the network edge to cloud servers with specific applications dedicated to high-performance computing (HPC). Additionally, we're seeing interest in RISC-V for general-purpose processors for laptops, desktops and data centers with vertical and horizontal scaling. 

Scott Matteson: What are your goals for the ecosystem?

Mark Himelstein: My goals for the RISC-V community are to expand collaboration and development across markets. In order to strengthen the community and access to RISC-V resources, I will aim to: Enable vertical markets from the systems software stack to the applications software stack; enable open-source and closed-source software from design verification (DV) to operating systems (OS) to applications and everything in between; and enable companies and individuals to easily share designs for silicon, soft intellectual property (IP), boards, systems, software, and more. 

Scott Matteson: What educational/training options are recommended?

Mark Himelstein: We encourage anyone interested in RISC-V to check out the educational material on our website where we have links to lectures, video tutorials and other helpful resources. Additionally, the global RISC-V community regularly hosts meetups (both in-person and online), where everyone has the opportunity to learn about RISC-V solutions, projects and implementations. 

Scott Matteson: What does the future look like for RISC-V?

Mark Himelstein: The future will see an explosion of applications that are designed with RISC-V. Our flexible and scalable designs, open-source licensing and modern design architecture (designed from the bottom-up) will fuel our growth in membership and planned deployments. We expect the beginning of volume deployments in the second half of 2021 and 2022. We have made incredible progress over the past few years, taking advantage of this unique moment in history. We have been able to build on 30 years of open-source software development and more than 40 years of ISAs and the resulting products. We hit the ground running, and there are now over 685 members of RISC-V International. There are over 90 RISC-V-based hardware products listed on our website from different companies, and there are a variety of off-the-shelf (OTS) dev boards under $50 for small embedded projects in addition to boards under $500 that run Linux. 

Scott Matteson: What resources do you recommend for learning more about RISC-V components and processes?

Mark Himelstein: The riscv.org website is a great place to learn more about the RISC-V ISA along with the available boards, cores, and SoCs that are available for designers. The site also lists out debugging, C compilers, configuration, verification tools, SDKs, and other software tools in the RISC-V ecosystem. The RISC-V GitHub page is an excellent resource as well. 

Additionally, RISC-V International recently announced the RISC-V Training Partner Program, which includes training offerings from a number of different organizations. Participants have the opportunity to expand the breadth of their RISC-V knowledge and learn more about the benefits of open collaboration. There are also a number of educational courses on RISC-V from universities around the world.  

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