Hi, I’m new here. I not sure exactly where to post this. So I apologize if this post is in the wrong section. I was informed by a friend that a majority of you guys are very clued about computer hardware related issues. I’m doing a Computer Science degree and I have an assignment due. Would anybody be able with some of these questions I’m having problems with :
1. Assume that one 16-bit and two 8-bit microprocessors are to be interface to a system bus. The following details are given: [25]
* All microprocessors have the hardware features necessary for any type of data transfer: Programmed I/O, interrupt-driven I/O, and DMA.
* All microprocessors have 16-bit address bus
* Two memory boards, each 64 Kbytes capacity, are interfaced with the bus. The designer wishes to use a shared memory that is as large as possible.
* The system bus supports a maximum of four interrupt lines and one DMA line.
Make any assumptions necessary, and
a) Give the system bus specifications in terms of number and type of lines.
b) Describe a possible protocol for communicating on the bus, i.e., read/write, interrupt and DMA sequences.
c) Explain how the aforementioned devices are interfaced to the system bus.
4. If you were designing a new computer with a new instruction set, what are the tradeoffs between code size and CPU complexity that would influence your choice of whether to use 0-operand, 1-operand, 2-operand or even 3-operand instructions. Use code fragments for computing X=(A/B-C)/(A+E*F) to illustrate your points. [15]
5. A computer designer decides to design a new type of CPU using the idea of Very Long Instruction Words. Instead of the current trend towards regular, reduced instruction set sizes, the idea is to have a small number of very complex instructions that can carry out a lot of operations in one go. The proposed instruction design has up to three operands which can be memory or register, and has two opcodes, which can be any combination of the logical or arithmetic instructions and/or/add/sub/div/mul, and a further operand which is the address of the next instruction to be fetched and executed.
i. Assuming a 32bit byte addressable memory architecture, how many bits might the typical instruction take? [7]
ii. What are the problems with this approach, and why is RISC preferred nowadays? [8]
