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  • #2189288

    Computer Organization & Architecture


    by neon5 ·

    Hi, I’m new here. I not sure exactly where to post this. So I apologize if this post is in the wrong section. I was informed by a friend that a majority of you guys are very clued about computer hardware related issues. I’m doing a Computer Science degree and I have an assignment due. Would anybody be able with some of these questions I’m having problems with :

    1. Assume that one 16-bit and two 8-bit microprocessors are to be interface to a system bus. The following details are given: [25]

    * All microprocessors have the hardware features necessary for any type of data transfer: Programmed I/O, interrupt-driven I/O, and DMA.

    * All microprocessors have 16-bit address bus

    * Two memory boards, each 64 Kbytes capacity, are interfaced with the bus. The designer wishes to use a shared memory that is as large as possible.

    * The system bus supports a maximum of four interrupt lines and one DMA line.
    Make any assumptions necessary, and
    a) Give the system bus specifications in terms of number and type of lines.
    b) Describe a possible protocol for communicating on the bus, i.e., read/write, interrupt and DMA sequences.
    c) Explain how the aforementioned devices are interfaced to the system bus.

    4. If you were designing a new computer with a new instruction set, what are the tradeoffs between code size and CPU complexity that would influence your choice of whether to use 0-operand, 1-operand, 2-operand or even 3-operand instructions. Use code fragments for computing X=(A/B-C)/(A+E*F) to illustrate your points. [15]

    5. A computer designer decides to design a new type of CPU using the idea of Very Long Instruction Words. Instead of the current trend towards regular, reduced instruction set sizes, the idea is to have a small number of very complex instructions that can carry out a lot of operations in one go. The proposed instruction design has up to three operands which can be memory or register, and has two opcodes, which can be any combination of the logical or arithmetic instructions and/or/add/sub/div/mul, and a further operand which is the address of the next instruction to be fetched and executed.

    i. Assuming a 32bit byte addressable memory architecture, how many bits might the typical instruction take? [7]
    ii. What are the problems with this approach, and why is RISC preferred nowadays? [8]

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    • #3069175

      I can’t answer that…

      by dc guy ·

      In reply to Computer Organization & Architecture

      But I appreciate the fact that you’re the first person I’ve ever encountered posting a question on a bulletin board who actually admits he wants the answer for a class assignment!

      You might want to post this under Tech Q&A. That’s where the real experts hang out.

      • #3069171

        Reply To: Computer Organization & Architecture

        by neon5 ·

        In reply to I can’t answer that…

        Ah that’s what I’m looking for. Thanks I’ll ask under there. Sorry for the inconvenience.

        Well I can’t exactly say it’s for err… my gran who wants to learn about computer architecture in terms of bit processing. He he.


    • #3069080


      by jmgarvin ·

      In reply to Computer Organization & Architecture

      Kudos! You actually said you need help with an assignment…a first on TR…a sure sign the world is ending. You might want to post this to Tech Q&A.

      I’d have to crack a book again, but here is what I’d say (off hand)

      a) You’d need at least a 16 bit bus to deal with all that, although I must admit I’m confused by what your instructor means by “type of lines.”

      b) I must say I’m not clear on this. I’d used a queued DMA schema or something of the like.

      c) I have no idea how to do this without cracking an architecture book.

      4) This looks like an induction proof. I’d have to say you are always going to see similar performance for all of them

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