Hello. Have anyone tried to use dual new 100 Mhz Celerons? Especially on Intel’s STL2. Yep, I know it’s a Server Board, but 100 Mhz is “serverish” enough — and FSB can be reduced to 100. There was a buzz about older secc Celerons not having any signal on their SMP pin BR1#. Have anything changed since that good-old time?
The new Celerons even need the same core voltage as identical 100 Mhz PIIIs. Maybe their difference is now only the cache size? And this carving on the BOX “single processing only” may be a marketing issue %))
Thank You in advance
P.S. I tried hard to find any info on Cel’s pinouts but… to no avail yet.
