Hardware

I have a question regarding the recommendations from MCP regarding the MCP3**1 analog front end (datasheet as reference: http://www.kynix.com/uploadfiles/pdf2286/MCP3**1A0-E2fML_70**9.pdf ). Specifically, the master clock has a maximum input rate of about 20MHz, whereas the maximum ADC clock rate (AMCLK) is specified to be 16MHz. Looking through the documentation provided by MCP on , it seems as if the SNR, SFDR, SINAD, THD, etc. for the MCP3**1 would actually be fine up to a 20MHz clock rate as long as boost has been set to 2x and gain = 1.
I presume there is a reason that MCP is showing the performance of the analog front end at frequencies that exceed the recommended limits but wonder why 16MHz was set as the AMCLK limit. Is perhaps the ADC not able to sample correctly at these frequencies? Or is it good design practice to leave several MHz of 'headroom' between the maximum frequency where performance degrades and the maximum recommended AMCLK frequency?

I apologize in advance if this is too simplistic a question. In the meantime, I'll happily use this great chip at 15MHz MCLK = AMCLK. Thank you!