On Monday, the Linux Foundation announced the formation of the CHIPS Alliance, described as a “project to host and curate high-quality open source code relevant to the design of… more efficient and flexible chip designs for use in mobile, computing, consumer electronics, and Internet of Things (IoT) applications.” This alliance centers around the continued development and adoption of RISC-V, an open Instruction Set Architecture (ISA) intended to supplant the use of Arm CPUs in a variety of applications.
The CHIPS Alliance–which was founded to provide microarchitecture implementations for use cases from microcontroller and IoT to datacenter applications–is a counterpart to the RISC-V Foundation, which controls the ISA specification and extensions to it.
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Of the announced contributions, Google is developing a Universal Verification Methodology (UVM) environment, which is “instruction stream generator environment… [providing] configurable, highly stressful instruction sequences that can verify architectural and micro-architectural corner-cases of designs,” according to the Linux Foundation.
Western Digital will contribute their previously-announced SweRV core, a 32-bit, 2-way superscalar, 9 stage pipeline core capable of clock speeds up to 1.8 GHz, plus a test bench and SweRV Instruction Set Simulator (ISS). WD will also release the specification and early implementation of OmniXtend, a “fully open networking protocol for exchanging coherence messages directly with processor caches,” which is intended for connecting persistent memory to processors.
SiFive, a company created by the inventors of RISC-V, is contributing the open-source Chisel hardware description language, the SoC parameter negotiation framework Diplomacy, and the RocketChip SoC generator, which includes the TileLink coherent interconnect fabric.
Why does RISC-V matter?
RISC-V is made available under the BSD license, and requires no patent royalties for implementation. Any organization that wishes to implement or extend RISC-V in commercial products can do so, without being required to disclose their changes to the community at large. This makes it particularly appealing for commercial use in embedded devices, as licensing fees for ARM or MIPS designs–both of which are fundamentally RISC in principle–do not need to be paid.
RISC-V has a great deal of momentum behind it, with SiFive’s Hi-Five single board computer available to developers. Western Digital is also committing to “shipping two billion RISC-V cores annually” once they have transitioned their designs to RISC-V, and NVIDIA is planning to use the ISA for the next-generation replacement for their Falcon microcontroller.
For more on the partnership between the Linux Foundation and RISC-V Foundation, check out TechRepublic’s previous coverage: RISC-V and Linux Foundations will partner to promote open source CPU.
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