Seeed Studio is bringing RISC-V capabilities to the Raspberry Pi with the Grove AI HAT for Edge Computing, a $25 add-on to the Raspberry Pi–sitting on top, connecting using the RPi’s GPIO connector pins–equipped with a Sipeed MAIX M1 AI Module, which utilizes a Kendryte K210 processor.

The Grove AI HAT includes six Grove interfaces, including one each for Digital I/O, PWM, I2C, and UART, and two ADC, as well as an interface for a single LCD and camera each, and a microphone and accelerometer onboard. It also integrates a USB-C 2.0 connector, a JTAG & ISP UART pin header, and two 20-pin headers for I2C, UART, SPI, I2S, PWM, and GPIO.

SEE: Inside the Raspberry Pi: The story of the $35 computer that changed the world (cover story PDF) (TechRepublic)

Sipeed compares the MAIX M1 AI Module to Google’s Edge TPU accelerator, though notes that it “acts as a master controller, not an accelerator,” making it a lower-cost and lower-power solution. MAIX, according to Sipeed, “can be used for a growing number of industrial use-cases such as predictive maintenance, anomaly detection, machine vision, robotics, voice recognition, and many more. It can be used in manufacturing, on-premise, healthcare, retail, smart spaces, transportation, etc.”

The K210, the CPU at the core of the MAIX M1, is a 28nm, 64-bit dual-core RISC-V IMAFDC design, with a neutral network processor capable of object recognition.

The Grove AI HAT can be pre-ordered for $24.50, though the price will increase modestly to $28.90 after June 15, 2019, when the device goes into general availability.

Why does RISC-V matter?

RISC-V is a freely-available instruction set architecture (ISA) made available under the BSD license, and requires no patent royalties for manufacture or implementation. Any group that wishes to implement or extend RISC-V in commercial products can do so, without being required to disclose their changes to the public. This makes it particularly appealing for commercial use in embedded devices, as manufacturers can save on licensing fees associated with ARM or MIPS ISAs–both of which are fundamentally RISC in principle.

RISC-V has a great deal of momentum behind it, with the Linux Foundation and the RISC-V Foundation partnering with Google and Western Digital to found the CHIPS Alliance to promote the adoption and development of RISC-V implementations. Western Digital, which has publicly committed to “shipping two billion RISC-V cores annually” on products the company manufactures, is opening its SweRV RISC-V implementation and associated tools.

For more on RISC-V, learn how to start developing for RISC-V with the $49, Arduino-compatible HiFive1, and learn about the high-performance, Linux-capable Hi-Five Unleashed single-board computer.