An Efficient Design of Vedic Multiplier using New Encoding Scheme

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Provided by: International Journal of Computer Applications
Topic: Hardware
Format: PDF
In this paper, the authors present a design of efficient digital Vedic multiplier using the Vedic sutras from ancient Indian Vedic mathematics. If they are looking towards the signal processing, they will find multipliers and adders plays a very important roll. In fact if they make their focus they can see speed of the digital signal processing systems is mainly dependent on multipliers and adders. A processor requires more hardware and processing time during multiplication rather than addition and subtraction. In this paper, they proposed a new digital Vedic multiplier structure based on a new encoding algorithm.
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