Design Scheme Considering Memory Cell Array Noise for Stacked Type MRAM with NAND Structured Cell

In this paper, design scheme considering memory cell array noise for stacked type NAND MRAM has been newly described. Memory cell array noise which is inherent to stacked type NAND MRAM is newly analyzed. This noise for read operation of 48mV is almost equal to the signal to selected WL of 50mV during read operation. 3 kinds of design method, the increase in distance between adjacent WLs, introduction of high-k insulating layer, and air gap, which can reduce the memory cell array noise has been newly proposed.

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