Integer addition is a universal building block and applications such as quad-precision floating-point or elliptic curve cryptography now demand precisions well beyond 64 bits. This paper explores the trade-offs between size, latency and frequency for pipelined large-precision adders on FPGA. It compares three pipelined adder architectures, the classical pipelined ripple-carry adder, a variation that reduces register count and an FPGA-specific implementation of the carry-select adder capable of providing lower latency additions at a comparable price.