Building a slide deck, pitch, or presentation? Here are the big takeaways:
- MIT has developed new IoT encryption chips that eliminate software computations, leading to 99.75% power reduction, 1/10th the memory usage, and 500 times the speed.
- The new chips are larger than previous versions because they have separated different kinds of mathematical processing onto different circuits, showing that application-specific hardware has vast advantages over software or general-purpose chips for certain applications.
Researchers at MIT have announced the creation of a new chip designed for IoT devices that is dedicated solely to public key encryption tasks.
The new chip shifts computation work away from encryption software, which often has a high power consumption cost. By handling encryption and decryption of public keys via hardware, the chips can execute tasks 500 times faster, all while reducing power consumption by 99.75% and using 1/10th of the memory.
While encryption-specific chips like the one designed by the MIT team are not new, a big part of this one is. Previous chips of this type could only use one type of elliptic curve, thus restricting their usefulness. Unlike those older types, the new chips can use any elliptic curve.
How MIT designed a universal elliptic-curve encryption chip
Elliptic-curve cryptography (ECC) is an incredibly complicated subject. Without getting deep in the weeds as to how it works, it’s enough to say that it’s the next generation of cryptography after RSA.
ECC’s biggest benefit is that it can offer more security with smaller keys, which means faster data transmission and lower storage requirements. As internet-connected devices proliferate, so do the needs for faster, low-energy encryption, which is exactly where ECC shines.
One of the core components of ECC is modular arithmetic, and specifically modular multiplication (multiplication is the first step in public-key encryption). The MIT chip has a circuit solely dedicated to modular multiplication, and it’s huge: Most modular multipliers can handle 16- or 32-bit values at a maximum, and MIT’s can handle 256.
That 256-bit max allows MIT’s chip to handle larger calculations without relying on additional circuits, reducing energy requirements and increasing speed.
MIT did make a size concession on its new chip, which has a 10% larger surface area than others like it, but with very good reason: It includes a circuit specifically for performing inversions, another integral part of ECC. The inversion circuit cuts the chip’s power consumption in half.
The last innovation featured in the MIT chip is the hardwiring of the datagram transport layer security protocol, which is commonly used in ECC. This particular integration eliminates much of the memory requirements of previous encryption chips.
Specialized hardware: The future?
Computing, especially secure computing, is becoming more intensive as time goes on. The Internet of Things is also leading to a revolution in application-specific hardware that creates demands poorly suited to universally designed chips, leaving much of the work to software that drains power and leads to poor battery life and performance.
ASICs and other specialized hardware that take the onus away from software are likely the future of computing, at least as far as peripheral hardware is concerned. And the market for peripheral hardware keeps getting larger.
- IoT security: What you should know, what you can do (free PDF) (TechRepublic)
- ROBOT exploit from 1998 resurrected, leaves top websites’ crypto vulnerable (ZDNet)
- Encrypting communication: Why it’s critical to do it well (TechRepublic)
- How Cloudflare uses lava lamps to encrypt the Internet (ZDNet)
- How quantum computing could create unbreakable encryption and save the future of cybersecurity (TechRepublic)