Start developing for RISC-V with the $49 HiFive1 Revision B

The revised version of the HiFive1 embedded development board from SiFive adds Wi-Fi and Bluetooth support on the Arduino-compatible board.

RISC-V: The open-source ISA aiming for Arm's domination of IoT and embedded devices The open source RISC-V ISA allows companies to build their own CPUs for IoT and embedded devices, without needing to pay royalties associated with Arm processors.

On Tuesday, SiFive introduced a modest upgrade to the HiFive1 single-board computer (SBC), which is now powered by the newly-released FE310-G002 revision of SiFive's E31 RISC-V core. The original HiFive1 and FE310-G000 were introduced in 2016.

The HiFive1 is 68 mm x 51 mm, 32-bit RISC-V development board, though it is intended for Internet of Things (IoT), Arduino, and real-time embedded applications. This is not a board on which developers should expect to run a desktop or server Linux distribution, like the Raspberry Pi 3 B+.

3ea0c69619fcf3f16db9f8c85514a89a4f2d9d00boardshifive1.jpg
Image: SiFive

The FE310-G002 adds a low-power sleep mode and a 3.3V always-on domain (increased from the 1.8V of the original), as well as a hardware I²C, and a second UART. It contains a 32-bit RV32IMAC core with 16 KB L1 instruction cache, 16 KB SRAM, and hardware multiply/divide. The chip runs at "320+ MHz," according to SiFive, and is touted as "among the fastest microcontrollers on the market."

SEE: Hiring kit: IoT developer (Tech Pro Research)

The HiFive1 Rev B adds a Segger J-Link debugger. With this, the HiFive1 appears as a mass storage device when attached to a PC, enabling drag-and-drop flash programming. With the addition of the ESP32 co-processor, the board includes Wi-Fi and Bluetooth capabilities.

SiFive offers a five-pack of the FE310-G002 chips for $25, a single HiFive1 Rev B for $49 when preordered, or a five-pack of the HiFive1 Rev B for $239 when preordered, all of which are available via Crowd Supply. Orders are expected to ship on April 16, 2019.

RISC-V is an open-source instruction set architecture (ISA) which requires no royalties to be paid when manufacturing RISC-V CPUs. The project aims to design chips that can replace Arm CPUs in a variety of use cases. SiFive was founded by the inventors of the RISC-V ISA. The initiative has the backing of the Linux Foundation, with the newly-formed CHIPS Alliance seeing code and specification donations from Google, NVIDIA, Western Digital, and others.

Also see

hifive.jpg
Image: SiFive

By James Sanders

James Sanders is a technology writer for TechRepublic. He covers future technology, including quantum computing, AI, and 5G, as well as cloud, security, open source, mobility, and the impact of globalization on the industry, with a focus on Asia.